Rather than jumping to a denser 5nm process, Biggish Blue stuck with Samsung’s 7nm node but enhanced it to meet customer demands for more speed. This means a better chance of feeding its wide SIMD engines with enough data to keep things ticking.

Power11 sticks with 16 cores per chip and up to 160MB of cache. Dual socket configurations now scale from 40 to 60 cores and the clocks have been nudged from 4.0GHz to 4.3GHz. Not exactly warp speed, but enough to make a difference when you're throwing server workloads at it.

The chip includes in-core MMA units (Multiply-Matrix-Accumulator) to beef up AI compute, and can also offload work to GPUs or ASICs using the new Spyre Accelerator framework. IBM reckons this architecture boosts performance by up to 50 per cent in smaller systems, with mid-tier setups seeing 30 per cent gains and the top-end boxes getting a 14 per cent uplift.

IBM managed to cram in 32 DDR5 ports per socket, quadrupling the bandwidth and capacity compared to Power10’s measly eight. It’s all cooled under a chunky copper heatsink, and the company is already eyeing DDR6 support for future platforms. The current memory system also plays nice with both DDR4 and DDR5.

Security types will be mildly pleased to know that IBM's added Quantum Safe Security, a feature aimed at preparing systems for whatever post-quantum apocalypse might be lurking around the corner. It's already rolled out in IBM’s Z mainframes and now finds a home in Power11.

As a teaser, IBM dangled its future Power chip which will use a so-called triplet architecture and borrow thermal design ideas from that next-gen project. Details were scarce, but it looks like Big Blue still thinks there’s life in the Power line yet.