Silicon photonics is the secret sauce for the blistering data pipes inside Nvidia’s next wave of AI servers, so TSMC has marshalled its packaging allies to hoover up the work.
Nvidia wheeled out its Spectrum-X switch using co-packaged optics at Hot Chips 2025, a first public nod that CPO is no longer vapour and real kit is on the way.
That demo planted a flag for a CPO rush, with networking and compute finally admitting copper cannot keep up without guzzling power.
As AI traffic balloons, silicon photonics becomes the obvious route to ultra-fast links, which is why Nvidia is set to cram it into the Rubin platform with 2.5D and 3D tricks like CoWoS and SoIC.
The plan is to blend photonics with likely CPO to ease electrical interconnect choke points and trim energy burn, because watts are the new enemy.
TSMC has been tooling up for this and used its 2025 North American Technology Forum to bang on about progress, highlighting a Compact Universal Photonics Engine that stacks electronic dies on photonic dies.
The COUPE approach targets the data deluge sparked by AI workloads, putting compute and light in tighter embrace so signals do not crawl.
TSMC wants COUPE verified in 2025, then folded into CoWoS in 2026 as co-packaged optical parts, pitching it as the jumper cables for AI’s next leap.
The foundry has cosied up further with Marvell on sub-3nm processes and next-gen photonics to widen the money pool.
Behind the scenes it has built a chunky optical comms database to speed designs, and the patent count shows the mood.
Patentfield tallies suggest TSMC filed 50 US silicon photonics applications in 2024, twice Chipzilla’s 26.
In 2023 they were neck and neck at 46 for TSMC and 43 for Chipzilla, but the long stretch used to belong to Intel by a mile.
Now TSMC has nosed ahead in filings and, according to industry chat, Chipzilla may lead in lab work yet lags in real deployments.
TSMC is lining up mass production of fresh CPO parts in 2026, while Chipzilla is still stuck in the R&D and demo lane.
TSMC is pulling its subsidiary Caiyu into the scrum, with talk of tighter integration across silicon photonics and CPO to give Caiyu’s books a lift.
Analysts say Caiyu’s wafer-level optical film chops suit receiver and transmitter alignment, optical boosting, and PIC integration, with metalenses to pep up customers’ coupling efficiency.
